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BU9832GUL-W (8Kbit)
Datasheet
● Notes on power ON/OFF
At power ON/OFF, set CS “H” (=Vcc).
When CS is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may
cause malfunction, mistake write or so. To prevent these, at power ON, set CS “H”. (When CS is in “H” status, all
inputs are canceled.)
Vcc
Vcc
GND
Vcc
CS
GND
Good example
Bad example
Figure 57. CS timing at power ON/OFF
(Good example)
(Bad example)
CS terminal is pulled up to Vcc.
At power OFF, take 10ms or higher before supply. If power is turned on without observing this condition,
t he IC internal circuit may not be reset, which please note.
CS terminal is “L” at power ON/OFF.
In this case, CS always becomes “L” (active status), and EEPROM may have malfunction, mistake
write owing to noises and the likes.
Even when CS input is High-Z, the status becomes like this case, which please note.
○ P.O.R. circuit
This IC has a P.O.R. (Power On Reset) circuit as mistake write countermeasure. After P.O.R. action, it gets in write
disable status. The P.O.R. circuit is valid only when power is ON, and does not work when power is OFF. When power is
ON, if the recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable
status owing to noises and the likes.
Vcc
tR
Recommended conditions of t R , t OFF , Vbot
t R
t OFF
Vbot
0
tOFF
Vbot
10ms or below
100ms or below
10ms or higher
10ms or higher
0.3V or below
0.2V or below
Figure 58. Rise waveform
● Noise countermeasures
○ Vcc noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
○ SCK noise
When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to
clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set
about 0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise
time (tR) of SCK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures.
Make the clock rise, fall time as small as possible.
○ WP noise
During execution of write status register command, if there exist noises on WP pin, mistake in recognition may occur
and forcible cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WP input. In the
same manner, a Schmitt trigger circuit is built in CS input, SI input and HOLD input too.
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? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
23/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001
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